1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device in which fuses provide settings for replacing defective addresses with redundant memory cells.
2. Description of the Related Art
In semiconductor memory devices, defective memory cells, if present, are replaced with redundant memory cells that serve as spare memory cells. Access to the addresses of the defective memory cells is switched over and directed to the redundant memory cells, thereby recovering the addresses of the defective memory cells. Semiconductor memory devices having large memory capacity are required to have high redundancy efficiency (defect recovery efficiency) in order to recover as many defects as possible. The redundancy efficiency can be increased by such a straightforward means as increasing the number of spares (redundant cells). On the other hand, however, it is also required to reduce the area size of a defect recovery system such as redundancy cells and redundancy circuitry and to improve the reliability of the redundancy system.
In order to replace defective memory cells with redundant memory cells, the addresses of the defective memory cells need to be recorded. Typical redundancy systems achieve this by providing fuses. Each fuse is associated with a latch circuit that serves to indicate the status of the fuse (severed/intact). In order to recover defective memory cells, spare column selecting lines and spare word lines are provided, for example, and a column selecting line and word line corresponding to a defective memory cell is replaced with a spare column selecting line and spare word line. Such implementation requires fuse latch circuits that store addresses with respect to both the column selecting line and the word line corresponding to the defective memory cell.
If a column selecting address is comprised of five bits, for example, five fuse latch circuits and one redundancy-check fuse latch circuit are provided. If a word selecting address is comprised of five bits, for example, five fuse latch circuits and one redundancy-check fuse latch circuit are provided. Here, the redundancy-check fuse latch circuit serves to indicate whether the corresponding spare column selecting line or corresponding spare word line is used or not. A set including the fuse latch circuits for storing addresses and the redundancy-check fuse latch circuit will hereinafter be referred to as a fuse set.
Fuses are severed with respect to defective addresses. Information about the severed fuses is supplied to the redundancy circuit via the fuse latch circuits, and is further supplied from the redundancy circuit to decoder circuits and driver circuits relating to column selecting lines and word lines. Based on this information, column selecting lines and word lines corresponding to the defective addresses are replaced with spare column selecting lines and spare word lines, which results in the defective memory cells being replaced.
In order to increase the redundancy efficiency (defect recovery efficiency), the spare column selecting lines and spare word lines may be doubled in number. This results in a need for twice as many fuse sets, which means twice as many fuse latch circuits. Fuse latch circuits are generally arranged in line, and corresponding fuses are also arranged in line. Pitches at which the fuse latch circuits are arranged are generally determined according to the fuse pitch.
If fuse sets are increased in number, the redundancy efficiency will proportionately be improved. However, this results in an increased number of fuses and fuse latch circuits, which contributes to an increase in area size. Since the pitches of fuse latch circuits are generally controlled by the fuse pitch, narrowing the fuse pitch makes it possible to decrease an area size penalty. Severing of fuses, however, requires the use of a laser beam. The smaller the fuse pitch, the higher the risk of having the severed fuse short-circuited to an adjacent fuse. Accordingly, while it is possible to narrow the fuse pitch to increase the redundancy efficiency and at the same time decrease an area size penalty, the reliability of fuses is sacrificed.